1. Field of the Invention
The present invention relates to the formation of capacitor structures over doped regions within semiconductor devices and, more particularly, to the formation of capacitor devices that store charge within dynamic random access memory devices.
2. Description of the Related Art
Further reductions in the size of memory cells within dynamic random access memory (DRAM) devices, and corresponding increases in the storage density of DRAMs, present a variety of challenges related to the reduced dimensions of the structures within the memory cell and in the increased processing difficulty associated with making such small structures. The typical DRAM memory cell consists of a charge storage capacitor electrically connected to the drain of a "pass" MOS transistor. The pass transistor acts as a switch for selectively coupling the charge storage capacitor to the memory cell's signal lines during data read out or write processes to respectively discharge or charge the capacitor. As DRAM memory cells are made smaller, efforts are made to reduce the size of the pass transistor and the capacitor, while maintaining the capacitance of the capacitor and thus keep constant the amount of charge stored in the memory cell. Consequently, as memory cell sizes decrease, the same amount of charge will flow through smaller and smaller pass transistors. Electrical field effects, including the short channel effect, become accentuated in such reduced-dimension pass transistors and become increasingly problematic when typical stored charge levels flow through such small pass transistors.
To reduce the difficulties associated with reduced-dimension pass transistors, it is desirable to manage the doping level and doping profile of the source and drain regions of the pass transistor. One frequently implemented strategy is the use of lightly doped drain (LDD) profiles for both the source and drain regions of the pass transistors. The adoption of such designs may not, however, ensure desired doping profiles in small source/drain regions because the dopants diffuse away from these regions when the device is subjected to high temperature processing steps after the formation of the source/drain regions. This problem is compounded when a DRAM capacitor is formed on the drain of the pass transistor by providing layers of doped polysilicon in contact with the drain region of the pass transistor. Such layers may be formed by depositing polysilicon over the memory cell region in contact with the drain region, implanting ions into the polysilicon, and then annealing the device to activate the implanted impurities and to render the polysilicon layer conductive. During this process, dopants from the polysilicon layer can diffuse into the substrate, creating a deeper and broader drain region than is desirable.
One strategy for addressing the problem of dopants diffusing from the polysilicon bottom electrodes of capacitors into the drain region is illustrated in FIGS. 1-4. FIGS. 1-4 show cross-sectional views of a portion of a DRAM memory cell at an early stage of manufacture. The illustrated memory cell is formed on a P-type substrate 10 and includes thick field oxide regions 12 to provide isolation from other, adjacent memory cells. A gate oxide layer 14 is formed by thermal oxidation on part of the active device region of the illustrated memory cell and a polysilicon gate electrode 16 is formed on the gate oxide layer 14. The polysilicon gate electrode 16 is formed by depositing a layer of undoped polysilicon over the substrate, typically using low pressure chemical vapor deposition (LPCVD), patterning the polysilicon using photolithography and then implanting impurities into the polysilicon and activating the impurities to render the gate electrode conductive. Polysilicon wiring line 18 is formed on the field oxide region 12 at the same time as the gate electrode 16.
Doped source/drain regions 19, 20 are formed on either side of the polysilicon gate electrode to define the channel region of the memory transistor. Generally, a lightly doped drain (LDD) structure is used in small design rule memory transistors of the type that are primarily used in modern memory and logic devices. LDD source/drain regions 19, 20 are typically formed in a two step process, beginning with a relatively low level dopant implantation made self-aligned to a polysilicon gate electrode 16. Subsequently, spacer oxide regions 22 are formed on either side of the gate electrode by first depositing a layer of CVD oxide over the device and then anisotropically etching back the oxide layer to expose the substrate over the source/drain regions 19, 20. Etching back the CVD oxide layer produces the spacer oxide regions 22 on either side of the polysilicon gate electrode 16 and on either side of the polysilicon wiring line 18. After the spacer oxide regions 22 are provided on either side of the polysilicon gate electrode 16, a second, heavier ion implantation is made into the source/drain regions 19, 20, self-aligned to the spacer oxide regions 22.
After the formation of the pass transistor of the memory cell, including the gate electrode 16 and the source/drain regions 19, 20, a layer 24 of insulation such as silicon oxide is deposited by chemical vapor deposition (CVD). An opening 26 is then formed by lithography through the layer 24 to expose the drain region 20 of the substrate, as shown in FIG. 2. Referring now to FIG. 3, a layer of undoped polysilicon 28 is deposited by low pressure chemical vapor deposition (LPCVD) over the surface of the device and within the opening 26 in contact with drain region 20. Layer 28 will form part of the lower electrode of the charge storage capacitor for the DRAM memory cell. A thin layer of native oxide, on the order of 3-4 .ANG. (not shown), is grown on the surface of polysilicon layer 28. Next, as shown in FIG. 4, a second layer 30 of polysilicon is deposited on the first undoped polysilicon layer 28. This layer is heavily doped with arsenic or phosphorus ions either in situ during the deposition process or by ion implantation. The native oxide layer over the surface of the first polysilicon layer 28 traps impurities during the implantation process so that the first polysilicon layer 28 remains substantially undoped. A subsequent anneal will cause impurities to diffuse through the polysilicon layers. By this process, relatively few dopants will diffuse into the drain region 20, so that the junction between the drain region 20 and the substrate 10 remains shallow. Subsequent processing patterns the two polysilicon layers 28, 30 to shape the bottom electrode, deposits an inter-electrode dielectric layer, and forms a doped polysilicon upper electrode.
The process illustrated in FIGS. 1-4 forms a conductive lower electrode for a charge storage capacitor in a manner that introduces relatively few additional impurities into the drain region 20. This structure, however, provides a lower electrode that is undesirably resistive. Such resistance internal to the capacitor can slow data read out and cause the loss of data. It is accordingly desirable to provide an improved process for forming a charge storage capacitor consistent with the formation of shallow junction source/drain regions for a DRAM cell's pass transistor.